Field of the Invention
The invention relates to a semiconductor device disposed in at least one semiconductor body and having at least one protection element for protecting an integrated semiconductor circuit against electrostatic discharge (ESD).
One such so-called electrostatic discharge (ESD) protection element is known from the article "Design and Layout of a High ESD Performance NPN Structure for Submicron BiCMOS/Bipolar Circuits", Proceeding of the IEEE International Reliability Physics Symposium (1996), pp. 227-32, J. Chen, X. Zhang, A. Amerasekera, T. Vrotsos.
Integrated semiconductor circuits in a chip include protective circuits to protect the inputs or outputs (I/O ports) against electrostatic overvoltages and the electrostatic discharges (ESD) caused thereby. These so-called ESD protection elements are connected between the input pad of an integrated semiconductor circuit and the input or output terminal to be protected. Thus an ESD protection element assures that, when a parasitic overvoltage occurs, the ESD protection element switches, and the parasitic overvoltage pulse is diverted to one of the supply potential conductor tracks. In an extreme case, such overvoltage pulses may destroy the component.
However, under operating conditions, described for instance in the product specification, the ESD protection elements must not impair the function of the integrated semiconductor circuit to be protected. This means that the switching voltage of the ESD protection element must be outside the signal voltage range of the protected terminal pads. To provide a good protective action, the ESC protection element should break through upstream of the most-critical circuit path. As a rule, this requires an exact adjustment of the switching voltage of the respective ESD protection element, under the essential boundary condition that the process control, which has been optimized with regard to the properties of the components of the integrated semiconductor circuit to be protected, is not changed by the addition of the ESD protection elements.
Another essential condition results from the spatial disposition of the terminal pads in the immediate vicinity of the integrated semiconductor circuit to be protected. In particular, because of the relatively high current to be driven, the terminal pads are located in the vicinity of the output drivers. The ESD protection structure is therefore often connected to the supply line supplying current to the output driver.
In protection elements having a pronounced snap-back behavior, such as thyristors and bipolar transistors, rapid switch-on events or unwanted pulses can cause a switching through, even though the breakdown voltage determined by measuring the characteristic curve in the low-current range is outside the specified signal voltage range. This is also known as transient latch-up effect which generally destroys the ESD protection element. The transient latch-up occurs particularly in smart power applications.
Therefore, despite high ESD strength and good protective action, such thyristors or bipolar transistors cannot be employed as ESD protection elements because of the transient latch-up. One is thus limited to using breakdown diodes or transistors with low gain. Yet these components have a much lower ESD strength.
For further details, characteristics, advantages and the modes of operation of ESD protective circuits, Published European Patent Application EP 0 623 958 Al and the aforementioned paper by J. Chen et al. are hereby incorporated by reference in their entirety.